The present invention relates generally to electronic circuits, and specifically to switching capacitor circuits.
Switched capacitors are one of the basic building blocks in analog circuitry. A switch, which couples a potential to a capacitor, closes to charge the capacitor to the potential. The switch then opens so that the charge remains on the capacitor. Typically, the switch is implemented from one or more transistors, such as metal oxide semiconductor (MOS) transistors. In this case, as the switch opens, there is a transfer of charge from the transistor to the capacitor. The charge transfer is caused by a combination of charge injection and clock feed-through. Charge injection is the charge in the channel of the transistor dissipating by leakage to the drain and/or the source of the transistor. Clock feed-through is the charge induced by the parasitic capacitance of the gate-diffusion overlap. Hereinbelow the combination is referred to by the single term xe2x80x9ccharge injection.xe2x80x9d As accuracy requirements for circuits become more stringent, the effect of charge injection error becomes correspondingly more problematic.
FIG. 1 is a schematic diagram of a circuit for reducing charge injection error, as is known in the art. The circuit comprises an n-channel MOS (NMOS) transistor 10 and a p-channel MOS (PMOS) transistor 12. Transistors 10 and 12 are coupled in parallel, with sources 14 connecting to each other, and drains 16 also connecting to each other. Transistor 10 is switched off by a CLK signal coupled to the gate of the transistor going low; transistor 12 is switched off by an inverse of CLK, coupled to the gate of transistor 12, going high. In this application and in the claims, a pair of NMOS and PMOS transistors coupled in this manner is termed a transmission gate switch. At switch-off time, charges in a channel 18 of transistor 12 and in a channel 20 of transistor 10 dissipate, as described above. Because the charges are opposite (since the majority carriers on transistor 10 are electrons and the majority carriers on transistor 12 are holes), they tend to cancel at dissipation.
The charges on the two transistors at switch-off are a function of a voltage Vin input to the transistors, and are also proportional to the areas of the respective gates. As is known in the art, it is possible to set the areas of the gates of each of transistors 10 and 12 so that the two charge injection errors cancel for a specific value of Vin. The cancellation is only valid to a first approximation, so that although the areas can be set so that the errors cancel for one value of Vin, at other values of Vin there is at best only partial cancellation.
FIG. 2 is a schematic electronic diagram of a circuit 26 for reducing charge injection, as is known in the art. A description of circuit 26 is given on pages 722 and 723 of CMOS Circuit Design, Layout, and Simulation by R. J. Baker et al., published by the IEEE Press, 1998, and is incorporated herein by reference. An NMOS transistor 28 switches, via a clock CLK, a voltage Vin charging a capacitor 32. A xe2x80x9cdummyxe2x80x9d switch 30, formed from a transistor having its drain and source shorted, is coupled to the line connecting transistor 28 to capacitor 32. Switch 30 is clocked by an inverse of CLK. The injection charge formed when transistor 28 switches off charges a capacitor formed by transistor 30 switching on. Unfortunately, optimal operation of circuit 26 is very dependent on the xe2x80x9cjitterxe2x80x9d between clocks of transistor 28 and transistor 30 being close to zero. Circuits such as those described with reference to FIG. 2, and transmission gate switches such as those described with reference to FIG. 1, can typically reduce injection charge voltage errors to approximately 5 mV for a dynamic input voltage range of the order of 1 V.
U.S. Pat. No. 5,479,121 to Shen et al., whose disclosure is incorporated herein by reference, describes a system for correcting problems caused by injection error charges. The system comprises a compensating circuit which includes an amplifier and two capacitors. A capacitance ratio of the capacitors is chosen so that when they function in combination with the amplifier, injection charge is effectively neutralized. However, the system does not correct the second order effect caused by the dependence of the charge injection error on the value of Vin, and is complicated.
In preferred embodiments of the present invention, a transmission gate switch receives an input voltage which charges a load capacitor. An output of the transmission gate switch is coupled to a sub-circuit which compensates for charge injection error caused when the transmission gate switch switches off. The sub-circuit comprises switching circuitry having a plurality of switches connected in series, including an isolating switch and a discharge switch. A pole of the isolating switch is coupled to the output of the transmission gate switch. A compensating capacitor is connected in parallel with the discharge switch. The plurality of switches are clocked so that when the injection error charge is generated, the compensating capacitor is coupled to the transmission gate switch and receives the error charges. At a later time, the capacitor is de-coupled from the transmission gate switch by the isolating switch, and is discharged by the discharge switch. The sub-circuit enables both first and second order injection charge errors to be substantially eliminated, so that an error voltage substantially less than 1 mV results over a dynamic input range greater than 1 V.
In some preferred embodiments of the present invention, the transmission gate switch operates in a differential mode, wherein first and second transmission gate switches receive complementary differential voltages. The differential voltages charge respective matched load capacitors. The compensation sub-circuit preferably comprises a first and a second isolating switch, each being connected to a respective output of one of the transmission gate switches. The discharge switch is connected in series to the first and a second isolating switches.
The sub-circuit utilizes a first clock which is an inverse of a clock operating the transmission gate switches. A second clock of the sub-circuit controls the discharge switch, the second clock being in phase with the transmission gate clock but having a different duty cycle. Since the injection charge error of the circuit is relatively insensitive to timing of the discharge, performance of the sub-circuit is substantially unaffected by jitter between the first and second clocks.
In some preferred embodiments of the present invention, the compensating capacitor is not a distinct element of the sub-circuit, but is implemented as a parasitic capacitance of the discharge switch, so that component count of the sub-circuit is reduced.
Preferably, at least some of the switches of the sub-circuit are transmission gate switches. Alternatively, at least some of the switches are single transistors.
There is therefore provided, according to a preferred embodiment of the present invention, a switched capacitor circuit, including:
a load-capacitor;
a charging switch, which is coupled to apply a potential to the load-capacitor;
a compensating-capacitor; and
switching circuitry, which is coupled to the charging switch and the compensating-capacitor and is switchable so as to transfer to the compensating-capacitor an injection error charge produced by the charging switch, and then to isolate the injection error charge on the compensating-capacitor from the load-capacitor.
Preferably, the switching circuitry includes an isolation switch which isolates the injection error charge from the load-capacitor.
Preferably, the circuit includes a clock which toggles the charging switch and the isolation switch substantially in anti-phase.
Preferably, the switching circuitry includes a discharge switch which discharges the compensating-capacitor, and the circuit preferably includes a first clock which toggles the charging switch and a second clock which toggles the discharge switch substantially in phase with the charging switch, wherein the second clock has a second duty cycle less than a first duty cycle of the first clock.
Preferably, the charging switch includes a transmission gate switch.
Preferably, the compensating-capacitor includes a parasitic capacitance of the switching circuitry.
Preferably, the charging switch includes a transistor having a gate-capacitance, wherein a compensating-capacitor-capacitance of the compensating-capacitor is substantially equal to half the gate-capacitance of the transistor.
Preferably, the switching circuitry includes at least one transmission gate switch.
Preferably, the switching circuitry includes at least one metal oxide semiconductor (MOS) transistor.
There is further provided, according to a preferred embodiment of the present invention, a method for reducing error in a switched capacitor circuit, including:
coupling a charging switch to apply a potential to a load-capacitor; and
switching a compensating-capacitor into electrical communication with the charging switch so as to store on the compensating-capacitor an injection error charge produced by the charging switch, thus isolating the injection error charge from the load-capacitor.
Preferably, switching the compensating-capacitor includes coupling an isolation switch to the charging switch, and isolating the compensating-capacitor from the load-capacitor with the isolation switch.
Preferably, coupling the isolation switch includes toggling the charging switch and the isolation switch substantially in anti-phase.
Preferably, switching the compensating-capacitor includes coupling a discharge switch to the compensating-capacitor, and discharging the compensating-capacitor with the discharge switch.
Further preferably, the method includes toggling the charging switch with a first clock and toggling the discharge switch substantially in phase with the charging switch with a second clock, wherein the second clock has a second duty cycle less than a first duty cycle of the first clock.
Preferably, the compensating-capacitor includes a parasitic capacitance of switching circuitry which is adapted to switch the compensating-capacitor.
Further preferably, the switching circuitry includes at least one transmission gate switch.
Preferably, the switching circuitry includes at least one metal oxide semiconductor (MOS) transistor.
There is further provided, according to a preferred embodiment of the present invention, a differential switched capacitor circuit, including:
a first load-capacitor;
a first charging switch, which is coupled to apply a first differential potential to the first load-capacitor;
a second load-capacitor;
a second charging switch, which is coupled to apply a second differential potential to the second load-capacitor;
a compensating-capacitor; and
switching circuitry, which is coupled to the first charging switch and the second charging switch and the compensating-capacitor, and is switchable so as to transfer to the compensating-capacitor a first injection error charge produced by the first charging switch and a second injection error charge produced by the second charging switch, and then to isolate the first injection error charge and the second injection error charge on the compensating-capacitor from the first and second load-capacitors.
Preferably, the switching circuitry includes a plurality of isolation switches which isolate the first and second injection error charges from the first and second load-capacitors.
Further preferably, the circuit includes a clock which toggles the first and second charging switches substantially in anti-phase to the plurality of isolation switches.
Preferably, the switching circuitry includes a discharge switch which discharges the compensating-capacitor.
Further preferably, the circuit includes a first clock which toggles the first and second charging switches and a second clock which toggles the discharge switch substantially in phase with the first and second charging switches, wherein the second clock has a second duty cycle less than a first duty cycle of the first clock.
Preferably, at least one of the first and second charging switches includes a transmission gate switch.
Preferably, the compensating-capacitor includes a parasitic capacitance of the switching circuitry.
Preferably, at least one of the first and second charging switches includes a transistor having a gate-capacitance, wherein a compensating-capacitor-capacitance of the compensating-capacitor is substantially equal to half the gate-capacitance of the transistor.
Preferably, the switching circuitry includes at least one transmission gate switch.
Preferably, the switching circuitry includes at least one metal oxide semiconductor (MOS) transistor.
Preferably, the first and second injection error charges are substantially equal in magnitude.
Further preferably, the first and the second differential potential are substantially equal in magnitude, and the magnitude of the first and the second differential potential includes a value between 0 V and a predetermined function of one or more rail voltages supplying the circuit.
There is further provided, according to a preferred embodiment of the present invention, a method for reducing error in a differential switched capacitor circuit, including:
coupling a first charging switch to apply a first differential potential to a first load-capacitor;
coupling a second charging switch to apply a second differential potential to a second load-capacitor; and
switching a compensating-capacitor into electrical communication with the first and second charging switches so as to store on the compensating-capacitor a first injection error charge produced by the first charging switch and a second injection error charge produced by the second charging switch, thus isolating the first and second injection error charges from the first and second load-capacitors.
Preferably, switching the compensating-capacitor includes isolating the first and second injection error charges from the first and second load-capacitors with a plurality of isolation switches.
Further preferably, isolating the first and second injection error charges includes toggling the first and second charging switches substantially in anti-phase to the plurality of isolation switches.
Preferably, switching the compensating-capacitor includes coupling a discharge switch to the compensating-capacitor and discharging the compensating-capacitor with the discharge switch.
Preferably, the method includes toggling the first and second charging switches with a first clock and toggling the discharge switch substantially in phase with the first and second charging switches with a second clock, wherein the second clock has a second duty cycle less than a first duty cycle of the first clock.
Preferably, the compensating-capacitor includes a parasitic capacitance of switching circuitry which is adapted to switch the compensating-capacitor.
Further preferably, the switching circuitry includes at least one transmission gate switch.
Preferably, the switching circuitry includes at least one metal oxide semiconductor (MOS) transistor.
Preferably, the first and second injection error charges are substantially equal in magnitude.
Further preferably, the first and the second differential potential are substantially equal in magnitude, wherein the magnitude of the first and the second differential potential includes a value between 0 V and a predetermined function of one or more rail voltages supplying the circuit.
The present invention will be more fully understood from the following detailed description of the preferred embodiments thereof, taken together with the drawings, in which: